In the manufacturing of electronic equipment, it is beneficial to test the proper operation of the manufactured electronic equipment in order to maintain an expected level of quality. Testing may be performed on individual electronic components, subsystems, and complete systems. The testing of subsystems and systems typically involves testing interconnections between electronic components. However, problems may be encountered when trying to perform such testing.
For example, testing of subsystems and systems typically requires that there be two-way communication between a test controller and one or more electronic components to be tested. By connecting a test controller and multiple electronic components together in a serial chain, the test controller may communicate with (e.g., test) each of the multiple electronic components without requiring a large number of interface connections on either the test controller or the multiple electronic components. However, if a break occurs at some point along the serial chain, the test controller will not be able to communicate with (e.g., test) any electronic components that are located on the opposite side of the break from the test controller. In such a case, the test controller will typically not be able to easily isolate the fault (i.e., the break), and thus more extensive testing may be required, which can be labor-intensive, time-consuming, and expensive.
One solution to the above-described fault isolation problem was developed by the Joint Test Action Group (JTAG) and is described in Institute of Electrical and Electronic Engineers (IEEE) Standard 1149.1 (IEEE Standard Test Access Port and Boundary-Scan Architecture). That is, IEEE Standard 1149.1 describes test logic that can be included in integrated circuits to provide standardized approaches to testing interconnections between integrated circuits after they have been assembled on a printed circuit board (PCB), and testing the integrated circuits themselves. The test logic includes a boundary-scan register and other building blocks and is serially accessed through a dedicated multi-pin test access port (TAP).
While IEEE Standard 1149.1 describes a fairly robust solution to the above-described fault isolation problem, it also results in significant increases in die area, pad loading, and pin count. Also, as data rates increase, boundary-scan register loads in accordance with IEEE Standard 1149.1 become very impractical. Furthermore, other methods (e.g., write/read comparison, calibration, wire test, etc.) already exist to test high-speed links in a system.
In view of the foregoing, it would be desirable to provide a technique for testing interconnections between electronic components which overcomes the above-described inadequacies and shortcomings.